A Routability-Aware Algorithm for Both Global and Local Interconnect Resource Test and Diagnosis of Xilinx SRAM-FPGAs

With increasing scale of Field Programmable Gate Arrays (FPGAs), architecture of interconnect resources (IRs) in FPGA is becoming more and more complicated. IR testing plays an important role to guarantee correct functionality of FPGAs. Usually, architecture of Global IRs is regular, while architecture of Local IRs is more complicated compared to Global IRs. In the paper, a generic IR model revealing the connection relationships for both Global and Local IRs in Xilinx series FPGAs is studied. A routability-aware algorithm based on the generic IR model is also presented. Test configurations (TCs) can be automatically generated by the proposed algorithm. Thus, both Global and Local IRs can be tested with identical method. Further, the algorithm is generic and independent of type and size of FPGAs. The algorithm is evaluated in Virtex series FPGAs. Experimental results demonstrate that the routing algorithm is applicable to Virtex series FPGAs with higher IR coverage achieved.